1 EDI8L24129V white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco 128kx24 sram 3.3 volt features 128kx24 bit cmos static random access memory array ? fast access times: 10, 12, and 15ns ? master output enable and write control ? ttl compatible inputs and outputs ? fully static, no clocks surface mount package ? 119 lead bga (jedec mo-163), no. 391 ? small footprint, 14mm x 22mm ? multiple ground pins for maximum noise immunity single +3.3v (5%) supply operation dsp memory solution ? motorola dsp5630x tm ? analog devices sharc tm pin configuration pin symbols the EDI8L24129V xx bc is a 3.3v, three megabit sram constructed with three 128kx8 die mounted on a multi-layer laminate substrate. with 10 to 15ns access times, x24 width and a 3.3v operating voltage, the EDI8L24129V is ideal for creating a single chip memory solution for the motorola dsp5630x (figure 3) or a two chip solution for the analog devices sharc tm dsp (figure 4). the single or dual chip memory solutions offer improved system performance by reducing the length of board traces and the number of board connections compared to using multiple monolithic devices. for example, the capacitance load on the data lines for the bga package is 58% less than a monolithic soj solution. the jedec standard 119 lead bga provides a 44% space savings over using 128kx8, 300mil wide sojs and the bga package has a maximum height of 100 mils compared to 148 mils for the soj packages. the bga package also allows the use of the same manufacturing and inspection techniques as the motorola dsp, which is also in a bga package. 1 2 3 4 5 6 7 a nc ao a1 a2 a3 a4 nc b nc a5 a6 e a7 a8 nc c i/012 nc nc nc nc nc i/00 d i/013 vcc gnd gnd gnd vcc i/01 e i/014 gnd vcc gnd vcc gnd i/02 f i/015 vcc gnd gnd gnd vcc i/03 g i/016 gnd vcc gnd vcc gnd i/04 h i/017 vcc gnd gnd gnd vcc i/05 i nc gnd vcc gnd vcc gnd nc j i/018 vcc gnd gnd gnd vcc i/06 k i/019 gnd vcc gnd vcc gnd i/07 l i/020 vcc gnd gnd gnd vcc i/08 m i/021 gnd vcc gnd vcc gnd i/09 n i/022 vcc gnd gnd gnd vcc i/010 o i/023 nc nc nc nc nc i/011 p nc a9 a10 w a11 a12 nc q nc a13 a14 g a15 a16 nc a?-a16 address inputs e chip enable w master write enable g master output enable dq?-dq23 common data input/ output vcc power (3.3v5%) gnd ground nc no connection pin names
2 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com EDI8L24129V july 1 9 99 rev eco absolute maximum ratings recommended operating conditions capacitance block diagram *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on any pin relative to vss -0.5v to 4.6v operating temperature ta (ambient) commercial 0c to + 70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 1.5 watts output current. 50 ma junction temperature, tj 175c parameter sym min typ max units supply voltage vcc 3.135 3.3 3.465 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.3 v input low voltage vil -0.3 -- 0.8 v (f=1.0mhz, vin=vcc or vss) these parameters are sampled, not 100% tested. parameter sym max unit address lines ca 8 pf data lines cd/q 10 pf write & output enable lines w, g 8 pf chip enable lines e?-e2 8 pf g e w mode output power x h x standby high z icc2,icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 truth table
3 EDI8L24129V white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco dc electrical characteristics ac test conditions parameter sym conditions min max units 10ns 12-15ns ns operating power supply current icc1 w= vil, ii/o = 0ma, 420 360 ma min cycle standby (ttl) supply current icc2 e > vih, vin < vil or 90 75 ma vin > vih, f=?mhz full standby cmos icc3 e > vcc-0.2v 10 10 ma supply current vin > vcc-0.2v or vin < 0.2v input leakage current ili vin = 0v to vcc 10 10 a output leakage current ilo v i/o = 0v to vcc 10 10 a output high volltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 8.0ma 0.4 0.4 v ac test circuit (note: for tehqz,tghqz and twlqz, figure 2) input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1
4 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com EDI8L24129V july 1 9 99 rev eco symbol 10ns 12ns 15ns parameter jedec alt. min max min max min max units read cycle time tavav trc 10 12 15 ns address access time tavqv taa 10 12 15 ns chip enable access time telqv tacs 10 12 15 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 5 6 7 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 5 6 7 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 5 6 7 ns note 1: parameter guaranteed, but not tested. ac characteristics - read cycle read cycle - w high, g, e low read cycle 2 - w high
5 EDI8L24129V white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco note 1: parameter guaranteed, but not tested. symbol 10ns 12ns 15ns parameter jedec alt. min max min max min max units write cycle time tavav twc 10 12 15 ns chip enable to end of write telwh tcw 8 9 9 ns teleh tcw 8 9 9 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 8 9 10 ns taveh taw 8 9 10 ns write pulse width twlwh twp 8 10 11 ns twleh twp 8 10 11 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 5 0 6 0 7 ns data to write time tdvwh tdw 6 6 7 ns tdveh tdw 6 6 7 ns output active from end of write (1) twhqx twlz 3 3 3 ns ac characteristics - write cycle write cycle - w controlled
6 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com EDI8L24129V july 1 9 99 rev eco write cycle 2 - e controlled
7 EDI8L24129V white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com july 1 9 99 rev eco part number speed package (ns) no. EDI8L24129V12bi 12 391 EDI8L24129V15bi 15 391 package no. 391 119 lead bga jedec mo-163 package description part number speed package (ns) no. EDI8L24129V10bc 10 391 edi8l24128v12bc 12 391 EDI8L24129V15bc 15 391 ordering information commercial (0c to +70c) industrial (-40c to +85c)
8 white electronic designs corporation ? westborough, ma 01581 ? (508) 366-5151 www.whiteedc.com EDI8L24129V july 1 9 99 rev eco figure 3 - interfacing the motorola dsp5630x dsp family with the EDI8L24129V (128kx24). interfacing the motorola dsp5630x dsp family with the EDI8L24129V (128k x 24) motorola dsp5630x address bus a23 - a0 databus d23 - d0 EDI8L24129V dq0-dq23 a16 - a0 e\ w\ g\ EDI8L24129V EDI8L24129V (128k x 24) (128k x 24) (128k x 24) a16 - a0 e\ w\ g\ a16 - a0 e\ w\ g\ aa0 aa1 aa2 aa3 wr/ rd/ dq0-dq23 dq0-dq23 notes: 1) in this example three 128k x 24 external memory arrays are shown, one for x data, one for y data and one for program. specific applications may require one, two or all three arrays. 2)any combination of aa0-aa3 may be used as chip selects. however, each chip select may only be used to select one memory array. EDI8L24129V (128k x 24) a16-a0 e\ w\ g\ dq16-23 dq8-15 dq0-7 EDI8L24129V (128k x 24) a16-a0 e\ w\ g\ dq16-23 dq8-15 dq0-7 analog adsp-2106xl address bus a31-a0 msx \ wr\ rd\ data bus d47-d0 (creating a 128k x 48 memory array) figure 4 - interfacing the 21060l or the 21062l to the EDI8L24129V, 119 bga (creating a 128kx48 memory array.
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